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10-bit integrated, multiformat sdtv/hdtv video decoder, rgb graphics digitizer, and 2:1 multiplexed hdmi/dvi interface ADV7441A rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2008 analog devices, inc. all rights reserved. features multiformat decoder four 10-bit analog-to-digital converters (adcs) adc sampling rates up to 170 mhz mux with 12 analog input channels scart fast blank sampling support ntsc/pal/secam color standards support 525p-/625p-component progressive scan formats support 720p-/1080i-/1080p-component hd formats support digitizes rgb graphics from vga to uxga rates (up to 1600 1200 @ 60 hz) vbi data slicer (including teletext) analog-to-hdmi fast switching mode dual high-definition multimedia interface (hdmi) rx 2:1 multiplexed hdmi receiver hdmi 1.3, dvi 1.0 225 mhz hdmi receiver repeater support high-bandwidth digital content protection (hdcp 1.3) 36-bit deep color support s/pdif (iec60958-compatible) digital audio output multichannel i 2 s audio output (up to 8 channels) adaptive equalizer for cable lengths up to 30 meters internal edid ram general highly flexible output interface stdi function support standard identification 2 any-to-any 3 3 color-space conversion matrices programmable interrupt request output pins applications advanced tvs pdp hdtvs lcd tvs (hdtv ready) lcd/dlp? rear projection hdtvs crt hdtvs lcos? hdtvs audio/video receivers (avr) lcd/dlp front projectors hdtv stbs with pvr dvd recorders with progressive scan input support general description the ADV7441A is a high quality multiformat video decoder and graphics digitizer with an integrated 2:1 multiplexed hdmi? receiver. the ADV7441A contains two main processing sections. the first section is the standard definition processor (sdp), which processes all types of pal, ntsc, and secam signals. the second section is the component processor (cp), which processes yprpb and rgb component formats, including rgb graphics. the cp also processes the video signals from the hdmi receiver. the ADV7441A can keep the hdcp link between a hdmi source and the selected hdmi port active in analog mode operation. this allows for fast switching between the analog and hdmi modes. as a decoder, the ADV7441A can convert pal, ntsc, and secam composite or s-video signals into a digital itu-r bt.656 format. it can also decode a component rgb or yprpb video signal into a digital ycrcb or rgb pixel output stream. the ADV7441A supports the 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i component video standards as well as many other hd and smpte standards. scart and overlay functionality are enabled by the ability of the ADV7441A to process cvbs and standard definition rgb signals simultaneously. as a graphics digitizer, the ADV7441A can digitize rgb graphics signals from vga to uxga rates and convert them to a digital rgb or ycrcb pixel output stream. the ADV7441A incorporates a dual-input hdmi 1.3-compatible receiver that supports hdtv formats up to 1080p and display resolutions up to uxga. the reception of encrypted video is possible with the inclusion of hdcp. the inclusion of adaptive equalization in the hdmi receiver ensures robust operation of the interface with cable lengths up to 30 meters. the hdmi receiver has advanced audio functionality, including a mute controller that prevents audible extraneous noise in the audio output. to facilitate professional applications, where hdcp processing and decryption is not required, a derivative part of the ADV7441A is available. this allows users who are not hdcp adopters to purchase the ADV7441A. see the ordering guide for details. fabricated using an advanced cmos process, the ADV7441A is available in a space-saving, 144-lead, surface-mount, rohs- compliant, plastic lqfp and is specified over the ?40c to +85c temperature range. www..net
ADV7441A rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 electrical characteristics ............................................................. 4 video specifications ..................................................................... 6 analog and hdmi specifications .............................................. 7 timing characteristics ................................................................ 8 timing diagrams .......................................................................... 9 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 package thermal performance ................................................. 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 functional overview ...................................................................... 14 analog front end ....................................................................... 14 hdmi receiver ........................................................................... 14 standard definition processor pixel data output modes .... 14 component processor pixel data output modes .................. 14 composite and s-video processing ......................................... 14 component video processing .................................................. 15 rgb graphics processing ......................................................... 15 general features ......................................................................... 15 theory of operation ...................................................................... 16 analog front end ....................................................................... 16 hdmi receiver ........................................................................... 16 standard definition processor ................................................. 16 component processor (cp) ...................................................... 17 vbi data processor .................................................................... 17 pixel output formatting................................................................ 18 register map architecture ........................................................ 22 typical connection diagram ....................................................... 23 recommended external loop filter components ................ 24 ad9388a/ADV7441A evaluation platform .............................. 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 7/08rev. spa to rev. b 5/08rev. sp0 to rev. spa changes to general description section ...................................... 1 change to clamp level (when locked) parameter, table 3 ...... 7 changes to standard definition processor pixel data output modes section ................................................................................. 14 changes to component processor pixel data output modes section ................................................................................. 14 changes to table 8 .......................................................................... 18 added table 9 .................................................................................. 18 added table 10 ............................................................................... 19 added table 11 ............................................................................... 20 added ad9388a/ADV7441A evaluation system section ....... 25 updated outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 26 10/07revision sp0: initial version www..net
ADV7441A rev. b | page 3 of 28 functional block diagram rxa_0 alsb sda scl fb sog yc and cvbs yprpb rgb cvbs soy hs_in/cs_in vs_in rxa_1 rxa_2 rxa_c rxb_c rxb_0 rxb_1 rxb_2 ddcb_scl ddcb_sd a ddca_sd a ddca_scl mux sampler sampler pll mux equalizer equalizer llc generation adc3 clamp sync processing and clock generation control interface i 2 c control and data control filter control control hs/cs, vs adc2 clamp adc1 clamp adc0 clamp analog interface 10 10 10 10 data recovery alignment hdmi decode de xor vs hs 4:2:2 to 4:4:4 conversion edid/repeater controller hdcp engine hdcp eeprom packet processor mux input matrix data processor cha chb chc cha chb chc cy chd embedded sync color space converter decimation and downsampling filters packet/ infoframe memory audio processing lrclk sclk i 2 s spdif macrovision detection standard autodetection free run output control vbi data recovery global control synthesized llc control gain control chroma re- sample chroma 2d comb (0x04 max) chroma filter chroma demod chroma digital fine clamp fast blank overlay control g b r fb sync extract line length predictor re- sample control av code insertion cti c-dnr fsc recovery standard definition processor output formatter gain control luma re- sample luma 2d comb (0x04 max) luma filter luma digital fine clamp 10 10 10 pixel data p10 to p19 int1 hs/cs vs/field de/field llc sfl/ sync_out/ int2 p20 to p29 p0 to p9 digital processing block component processor sync source and polarity detect program delay noise and calibration active peak and hsync depth gain control digitial fine clamp macrovision ? and cgms detection offset address av code insertion standard identification sync extract vbi decoder ancillary data formatter ancillary data vbi data processor 0 6914-001 mclkout mda mcl figure 1. www..net
ADV7441A rev. b | page 4 of 28 specifications electrical characteristics avdd = 1.71 v to 1.89 v, dvdd = 1.62 v to 1.98 v, dvddio = 2.97 v to 3.63 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.135 v to 3.465 v , cvdd = 1.71 v to 1.89 v. operating temperature range is ?40c to +85c, unless otherwise noted. table 1. parameter 1 symbol test conditions min typ max unit static performance 2 resolution (each adc) n 10 bits integral nonlinearity inl bsl 27 mhz (@ a 10-bit level) ?0.5/+2 ?4/+6 lsb bsl 54 mhz (@ a 10-bit level) ?0.5/+2 lsb bsl 74 mhz (@ a 10-bit level) ?0.5/+1.5 lsb bsl 110 mhz (@ a 10-bit level) ?0.7/+2 lsb bsl 170 mhz (@ an 8-bit level) ?0.25/+0.5 lsb differential nonlinearity dnl at 27 mhz (@ a 10-bit level) ?0.5/+0.5 ?0.95/+2 lsb at 54 mhz (@ a 10-bit level) 0.5 lsb at 74 mhz (@ a 10-bit level) 0.5 lsb at 110 mhz (@ a 10-bit level) 0.5 lsb at 170 mhz (@ an 8-bit level) ?0.25/+0.2 lsb digital inputs input high voltage 3 v ih 2 v hs_in/cs_in, vs_in low trigger mode 0.7 v input low voltage 3 v il 0.8 v hs_in/cs_in, vs_in low trigger mode 0.3 v input current i in pin 21 ( reset ) ?60 +60 a all input pins other than pin 21 ?10 +10 a input capacitance 4 c in 10 pf digital outputs output high voltage 5 v oh i source = 0.4 ma 2.4 v output low voltage 5 v ol i sink = 3.2 ma 0.4 v high impedance leakage current i leak 10 a output capacitance 4 c out 20 pf power requirements 4 digital core power supply dvdd 1.62 1.8 1.98 v digital i/o power supply dvddio 2.97 3.3 3.63 v pll power supply pvdd 1.71 1.8 1.89 v analog power supply avdd 1.71 1.8 1.89 v terminator power supply tvdd 3.135 3.3 3.465 v comparator power supply cvdd 1.71 1.8 1.89 v digital core supply current i dvdd cvbs input sampling @ 54 mhz 6 140 189 ma graphics rgb sampling @ 108 mhz 6 141 252 ma scart rgb fast blank sampling @ 54 mhz 6 152 205 ma yprpb 1080p sampling @ 148.5 mhz 6 203 263 ma hdmi rgb sampling @ 165 mhz 7 , 8 242 329 ma hdmi rgb sampling @ 225 mhz 7 , 8 242 326 ma digital i/o supply current i dvddio cvbs input sampling @ 54 mhz 6 16 48 ma graphics rgb sampling @ 108 mhz 6 17 37 ma scart rgb fast blank sampling @ 54 mhz 6 16 50 ma yprpb 1080p sampling @ 148.5 mhz 6 42 61 ma hdmi rgb sampling @ 165 mhz 7 , 8 17 34 ma hdmi rgb sampling @ 225 mhz 7 , 8 20 34 ma www..net
ADV7441A rev. b | page 5 of 28 parameter 1 symbol test conditions min typ max unit hdmi comparators i cvdd cvbs input sampling @ 54 mhz 6 56 78 ma tmds pll and equalizer graphics rgb sampling @ 108 mhz 6 56 78 ma supply current scart rgb fast blank sampling @ 54 mhz 6 56 79 ma yprpb 1080p sampling @ 148.5 mhz 6 56 79 ma hdmi rgb sampling @ 165 mhz 7 , 8 86 105 ma hdmi rgb sampling @ 225 mhz 7 , 8 95 118 ma analog supply current 9 i avdd cvbs input sampling @ 54 mhz 6 63 102 ma graphics rgb sampling @ 108 mhz 6 174 278 ma scart rgb fast blank sampling @ 54 mhz 6 225 348 ma yprpb 1080p sampling @ 148.5 mhz 6 180 284 ma hdmi rgb sampling @ 165 mhz 7 , 8 0 2 ma hdmi rgb sampling @ 225 mhz 7 , 8 0 2 ma terminator supply current i tvdd cvbs input sampling @ 54 mhz 6 12 18 ma graphics rgb sampling @ 108 mhz 6 12 18 ma scart rgb fast blank sampling @ 54 mhz 6 12 18 ma yprpb 1080p sampling @ 148.5 mhz 6 12 18 ma hdmi rgb sampling @ 165 mhz 7 , 8 , 10 42 47 ma hdmi rgb sampling @ 225 mhz 7 , 8 , 10 63 69 ma audio and video pll supply current i pvdd cvbs input sampling @ 54 mhz 6 18 23 ma graphics rgb sampling @ 108 mhz 6 14 21 ma scart rgb fast blank sampling @ 54 mhz 6 17 23 ma yprpb 1080p sampling @ 148.5 mhz 6 19 24 ma hdmi rgb sampling @ 165 mhz 7 , 8 10 19 ma hdmi rgb sampling @ 225 mhz 7 , 8 15 20 ma power-down current i pwrdn 11.6 ma power-up time t pwrup 25 ms 1 the minimum/maximum specifications are guaranteed over the ?40c to +85c temperature range (t min to t max ). 2 all adc linearity tests were performed at input range full scale ? 12.5% and at zero scale + 12.5%. 3 pin 1, pin 105, pin 106, and pin 144 are 5 v tolerant. 4 guaranteed by characterization. 5 the v oh and v ol levels were obtained using the default drive strength value (0x15) in user map register 0xf4. 6 current measurements for analog inputs were made with hdmi/analog simultaneous mode disabled (user map register 0xba, bit 7 pr ogrammed with value 0) and with no hdmi sources connected to the part. 7 current measurements for hdmi inputs were made with a source co nnected to the active hdmi port and with no source connected to the inactive hdmi port. 8 audio stream is a noncompressed stereo audio sampling frequency of f s = 48 khz, and mclkout = 256 f s . 9 analog current measurements for cvbs were made with only adc0 powered up; for rgb, with only adc0, adc1, and adc2 powered up; for scart fb, with all adcs powered up; and for hdmi mode, with all adcs powered off. 10 the terminator supply current may vary with the hdmi source in use. www..net
ADV7441A rev. b | page 6 of 28 video specifications avdd = 1.71 v to 1.89 v, dvdd = 1.62 v to 1.98 v, dvddio = 2.97 v to 3.63 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.135 v to 3.465 v , cvdd = 1.71 v to 1.89 v. operating temperature range is ?40c to +85c, unless otherwise noted. table 2. parameter 1 , 2 symbol test conditions min typ max unit nonlinear specifications differential phase dp cvbs input, modulated in five steps 0.3 degrees differential gain dg cvbs input, modulated in five steps 0.6 % luma nonlinearity lnl cvbs input, five steps 0.8 % noise specifications snr unweighted luma ramp 61.8 db luma flat field 63.1 db analog front-end crosstalk 60 db lock time specifications horizontal lock range ?5 +5 % vertical lock range 40 70 hz f sc subcarrier lock range 1.3 khz color lock-in time 60 lines synchronization depth range 3 20 200 % color burst range 5 200 % vertical lock time 2 fields horizontal lock time 100 lines chroma specifications hue accuracy hue 1 degrees color saturation accuracy cl_ac 1 % color agc range 5 400 % chroma amplitude error 0.5 % chroma phase error 0.1 degrees chroma luma intermodulation 0.3 % luma specifications luma brightness accuracy cvbs, 0.5 v input 1 % luma contrast accuracy cvbs, 0.5 v input 1 % 1 the minimum/maximum specifications are guaranteed over the ?40c to +85c temperature range (t min to t max ). 2 guaranteed by characterization. 3 nominal synchronization depth is 300 mv at 100% of the synchronization depth range. www..net
ADV7441A rev. b | page 7 of 28 analog and hdmi specifications avdd = 1.71 v to 1.89 v, dvdd = 1.62 v to 1.98 v, dvddio = 2.97 v to 3.63 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.135 v to 3.465 v , cvdd = 1.71 v to 1.89 v. operating temperature range is ?40c to +85c, unless otherwise noted. table 3. parameter 1 , 2 test conditions min typ max unit clamp circuitry external clamp capacitor 0.1 f input impedance (except pin 74) clamps switched off 10 m input impedance of pin 74 20 k common-mode level (cml) 0.88 v adc full-scale level cml + 0.5 v adc zero-scale level cml ? 0.5 v adc dynamic range 1 v clamp level (when locked) cvbs input cml C 0.122 v scart rgb input (r, g, b signals) cml C 0.167 v s-video input (y signal) cmlC 0.122 v s-video input (c signal) cml v component input (y signal) cml ? 0.120 v component input (pr signal) cml v component input (pb signal) cml v pc rgb input (r, g, b signals) cml ? 0.120 v large clamp source current sdp only 8 ma large clamp sink current sdp only 8 ma fine clamp source current sdp only 0.25 a fine clamp sink current sdp only 0.4 a hdmi specifications 3 intrapair (positive-to-negative) differential input skew 0.4 t bit 4 channel-to-channel differential input skew 0.2 t pixel 5 + 1.78 ns 1 the minimum/maximum specifications are guaranteed over the ?40c to +85c temperature range (t min to t max ). 2 guaranteed by characterization. 3 guaranteed by design. 4 t bit is 1/10 the pixel period t pixel . 5 t pixel is the period of the tmds clock. www..net
ADV7441A rev. b | page 8 of 28 timing characteristics avdd = 1.71 v to 1.89 v, dvdd = 1.62 v to 1.98 v, dvddio = 2.97 v to 3.63 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.135 v to 3.465 v , cvdd = 1.71 v to 1.89 v. operating temperature range is ?40c to +85c, unless otherwise noted. table 4. parameter 1 , 2 symbol test conditions min typ max unit system clock and crystal crystal nominal frequency 28.6363 mhz crystal frequency stability 50 ppm horizontal sync input frequency 14.8 110 khz llc frequency range 12.825 170 mhz i 2 c ports (fast mode) 3 xcl frequency 4 400 khz xcl minimum pulse width high 4 t 1 0.6 s xcl minimum pulse width low 4 t 2 1.3 s hold time (start condition) t 3 0.6 s setup time (start condition) t 4 0.6 s xda setup time 4 t 5 100 ns xcl and xda rise times 4 t 6 300 ns xcl and xda fall times 4 t 7 300 ns setup time for stop condition t 8 0.6 s i 2 c ports (normal mode) 3 xcl frequency 4 100 khz xcl minimum pulse width high 4 t 1 4 s xcl minimum pulse width low 4 t 2 4.7 s hold time (start condition) t 3 4 s setup time (start condition) t 4 4.7 s xda setup time 4 t 5 250 ns xcl and xda rise times 4 t 6 1000 ns xcl and xda fall times 4 t 7 300 ns setup time for stop condition t 8 4 s reset feature reset pulse width 5 ms clock outputs llc mark space ratio t 9 :t 10 45:55 55:45 % duty cycle data and control outputs data output transition time sdr (sdp) 5 t 11 negative clock edge to start of valid data 3.4 ns t 12 end of valid data to negative clock edge 2.4 ns data output transition time sdr (cp) 6 t 13 end of valid data to negative clock edge 2 ns t 14 negative clock edge to start of valid data 0.5 ns i 2 s port (master mode) sclk mark space ratio t 15 :t 16 45:55 55:45 % duty cycle lrclk data transition time t 17 end of valid data to negative sclk edge 10 ns t 18 negative sclk edge to start of valid data 10 ns i2sx data transition time 7 t 19 end of valid data to negative sclk edge 5 ns t 20 negative sclk edge to start of valid data 5 ns mclkout frequency 4.096 24.576 mhz 1 the minimum/maximum specifications are guaranteed over the ?40c to +85c temperature range (t min to t max ). 2 guaranteed by characterization. 3 refers to all i 2 c pins (ddc and control port). 4 the prefix x refers to pin names beginning with s, ddca_s, and ddcb_s. 5 sdp timing figures were obtained usin g the default drive strength value (0x1 5) in user map register 0xf4. 6 cp timing figures were obt ained using the maximum drive strength valu e (0x3f) in user map register 0xf4. 7 the suffix x refers to pin names ending with 0, 1, 2, and 3. www..net
ADV7441A rev. b | page 9 of 28 timing diagrams xda xcl t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 notes 1. the prefix x refers to pin names beginning with s, ddca_s, and ddcb_s. 06914-002 figure 2. i 2 c timing llc p0 to p29, vs, hs, de/field, s fl/sync_out t 9 t 11 t 12 t 10 06914-003 figure 3. pixel port and control sdr output timing (sdp core) t 9 llc p0 to p29, vs, hs, de/field t 13 t 14 t 10 06914-004 figure 4. pixel port and control sdr output timing (cp core) sclk lrclk i2sx left-justified mode i2sx right-justified mode i2sx i 2 s mode msb msb ? 1 t 15 t 16 t 17 t 19 t 20 t 18 msb msb ? 1 lsb msb t 19 t 20 t 19 t 20 notes 1. the suffix x refers to pin names ending with 0, 1, 2, and 3. 06914-007 figure 5. i 2 s timing www..net
ADV7441A rev. b | page 10 of 28 absolute maximum ratings thermal resistance table 5. parameter rating avdd to agnd 2.2 v dvdd to dgnd 2.2 v pvdd to pgnd 2.2 v dvddio to dgnd 4 v cvdd to cgnd 2.2 v tvdd to tgnd 4 v dvddio to avdd ?0.3 v to +3.6 v dvddio to tvdd ?3.6 v to +3.6 v dvddio to dvdd ?2 v to +2 v cvdd to dvdd ?2 v to +0.3 v pvdd to dvdd ?2 v to +0.3 v avdd to cvdd ?2 v to +2 v avdd to pvdd ?2 v to +2 v avdd to dvdd ?2 v to +0.3 v avdd to tvdd ?3.6 v to +0.3 v tvdd to dvdd ?2 v to +2 v digital inputs voltage to dgnd dgnd ? 0.3 v to dvddio + 0.3 v digital outputs voltage to dgnd dgnd ? 0.3 v to dvddio + 0.3 v analog inputs voltage to agnd agnd ? 0.3 v to avdd + 0.3 v maximum junction temperature (t j _ max ) 125c storage temperature range ?65c to +150c infrared reflow, soldering (20 sec) 260c table 6. package type jt 1 unit 144-lead lqfp (st-144) 1.62 c/w 1 junction-to-package surf ace thermal resistance. package thermal performance to reduce power consumption during ADV7441A operation, turn off unused adcs. on a four-layer pcb that includes a solid ground plane, the value of ja is 25.3c/w. however, due to variations within the pcb metal and, therefore, variat ions in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement te chnique is to use the surface temperature of the package to estimate the die temperature, because this is not affected by the variance associated with the value of ja . the maximum junction temperature (t j _ max ) of 125c must not be exceeded. the following equation calculates the junction temperature using the measured surface temperature of the package and applies only when no heat sink is used on dut: t j _ max = t s + ( jt w total ) where: t s is the surface temperature of the package expressed in degrees celsius. jt is the junction-to-package surface thermal resistance. w total = {( av d d iavdd ) + ( dvdd idvdd ) + ( dvddio idvddio ) + ( pvdd ipvdd ) + ( cvdd icvdd ) + ( tvdd itvdd )}. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. contact an analog devices, inc., sales representative or send an e-mail to video.products@analog.com for more information on package thermal performance. esd caution www..net
ADV7441A rev. b | page 11 of 28 pin configuration and function descriptions pin 1 1 ddcb_sda 2 spdif 3 i2s0 4 i2s1 5 i2s2 6 i2s3 7 lrclk 8 sclk 9 mclkout 10 ext_clamp 11 sda 12 scl 13 alsb 14 dgnd 15 dvddio 16 de/field 17 hs/cs 18 vs/field 19 int1 20 s fl/sync_out/int2 21 reset 22 dgnd 23 dvdd 24 p0 25 p1 26 p2 27 p3 28 p4 29 p5 30 p6 31 p7 32 p8 33 p9 34 dgnd 35 dvddio 36 p10 73 test0 74 fb 75 sog 76 ain7 77 ain1 78 ain8 79 ain2 80 ain9 81 ain3 82 agnd 83 agnd 84 avdd 85 refout 86 cml 87 agnd 88 avdd 89 test2 90 refn 91 test3 92 refp 93 ain10 94 ain4 95 ain11 96 ain5 97 soy 98 ain12 99 ain6 100 pgnd 101 pvdd 102 audio_elpf 103 cgnd 104 cvdd 105 ddca_scl 106 ddca_sda 107 test4 108 test5 109 cvdd 110 cgnd 111 tvdd 112 rxa_cn 113 rxa_cp 114 tgnd 115 rxa_0n 116 rxa_0p 117 tgnd 118 rxa_1n 119 rxa_1p 120 tgnd 121 rxa_2n 122 rxa_2p 123 tvdd 124 rterm 125 cvdd 126 cgnd 127 tvdd 128 rxb_cn 129 rxb_cp 130 tgnd 131 rxb_0n 132 rxb_0p 133 tgnd 134 rxb_1n 135 rxb_1p 136 tgnd 137 rxb_2n 138 rxb_2p 139 tvdd 140 cgnd 141 cvdd 142 dvdd 143 dgnd 144 ddcb_scl 37 p11 38 p12 39 p13 40 p14 41 p15 42 p16 43 p17 44 p18 45 p19 46 p20 47 p21 48 ext_clk 49 dgnd 50 dvddio 51 llc 52 p22 53 p23 54 p24 55 p25 56 dgnd 57 dvdd 58 p26 59 p27 60 p28 61 p29 62 vs_in 63 hs_in/cs_in 64 dgnd 65 xtal1 66 xtal 67 dvddio 68 pvdd 69 pgnd 70 elpf 71 pvdd 72 pgnd ADV7441A top view (not to scale) 06914-005 figure 6. pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description 14, 22, 34, 49, 56, 64, 143 dgnd g digital ground. 82, 83, 87 agnd g analog ground. 69, 72, 100 pgnd g pll ground. 103, 110, 126, 140 cgnd g comparator ground. 114, 117, 120, 130, 133, 136 tgnd g terminator ground. 15, 35, 50, 67 dvddio p digital i/o supply voltage (3.3 v). 23, 57, 142 dvdd p digital core supply voltage (1.8 v). 84, 88 avdd p analog supply voltage (1.8 v). 68, 71, 101 pvdd p audio and video pll supply voltage (1.8 v). 104, 109, 125, 141 cvdd p hdmi comparator, tmds pll, and equalizer supply voltage (1.8 v). 111, 123, 127, 139 tvdd p terminator supply voltage (3.3 v). 74 fb i fast blank. fast switch overlay between cvbs and rgb analog signals. 73, 91, 108 test0, test3, test5 i test pins. do not connect. 89 test2 o test pin. do not connect. www..net
ADV7441A rev. b | page 12 of 28 pin no. mnemonic type 1 description 107 test4 i/o test pin. do not connect. 76 to 81, 93 to 96, 98, 99 ain1 to ain12 i analog video input channels. 24 to 33, 36 to 47, 52 to 55, 58 to 61 p0 to p29 o video pixel output port. 19 int1 o interrupt signal. can be active low or active high. the set of events that triggers an interrupt is under user control. 20 sfl/sync_out/int2 o subcarrier frequency lock (sfl). contains a serial output stream that can be used to lock the subcarrier frequency when this de coder is connected to any analog devices digital video encoder. sliced synchronization output signal (syn c_out). available only in cp mode. interrupt signal (int2). 17 hs/cs o horizontal synchronization outp ut signal (hs). output by the sdp and cp. composite synchronization (cs). a single signal containing both horizontal and vertical synchronization pulses. 18 vs/field o vertical synchronization output signal (vs). output by the sdp and cp. field synchronization output signal (field). field synchronization output signal in all interlaced video modes. 16 de/field o data enable signal (de). indicates active pixel data. field synchronization output signal (field). field synchronization output signal in all interlaced video modes. 11 sda i/o i 2 c port serial data input/output pin. sda is the data line for the control port. 12 scl i i 2 c port serial clock input. (maximum clock rate of 400 khz.) scl is the clock line for the control port. 13 alsb i this pin sets the second lsb of the slave address for each ADV7441A register map. 21 reset i system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the ADV7441A circuitry. 51 llc o line-locked output clock for pixel data. range is 13.5 mhz to 170 mhz. 65 xtal1 o this pin should be connected to the 28.63636 mh z crystal or left as a no connect if an external 3.3 v 28.63636 mhz clock oscillator source is used to clock the ADV7441A. in crystal mode, the crystal must be a fundamental crystal. 66 xtal i input pin for the 28.63636 mhz crystal. this pin can be overdriven by an external 3.3 v 28.63636 mhz clock oscillator source to clock the ADV7441A. 70 elpf o the recommended external loop filter must be connected to this elpf pin. 102 audio_elpf o the recommended external loop filter must be connected to this audio_elpf pin. 85 refout o internal voltage reference output. 86 cml o common-mode level for the internal adcs. 90 refn o internal voltage reference output. 92 refp o internal voltage reference output. 63 hs_in/cs_in i hs input signal. used in analog mode for 5-wire timing mode. cs input signal. used in analog mode for 4-wire timing mode. for optimal performance, a 100 series resistor is recommended on the hs_in/cs_in pin. 62 vs_in i vs input signal. used in analog mode for 5-wire timing mode. for optimal performance, a 100 series resistor is recommended on the vs_in pin. 75 sog i synchronization-on-green input. this pin is used in embedded synchronization mode. 97 soy i synchronization-on-luma input. this pi n is used in embedded synchronization mode. 112 rxa_cn i digital input clock complement of port a in the hdmi interface. 113 rxa_cp i digital input clock true of port a in the hdmi interface. 115 rxa_0n i digital input channel 0 complement of port a in the hdmi interface. 116 rxa_0p i digital input channel 0 true of port a in the hdmi interface. 118 rxa_1n i digital input channel 1 complement of port a in the hdmi interface. 119 rxa_1p i digital input channel 1 true of port a in the hdmi interface. 121 rxa_2n i digital input channel 2 complement of port a in the hdmi interface. 122 rxa_2p i digital input channel 2 true of port a in the hdmi interface. www..net
ADV7441A rev. b | page 13 of 28 pin no. mnemonic type 1 description 128 rxb_cn i digital input clock complement of port b in the hdmi interface. 129 rxb_cp i digital input clock true of port b in the hdmi interface. 131 rxb_0n i digital input channel 0 complement of port b in the hdmi interface. 132 rxb_0p i digital input channel 0 true of port b in the hdmi interface. 134 rxb_1n i digital input channel 1 complement of port b in the hdmi interface. 135 rxb_1p i digital input channel 1 true of port b in the hdmi interface. 137 rxb_2n i digital input channel 2 complement of port b in the hdmi interface. 138 rxb_2p i digital input channel 2 true of port b in the hdmi interface. 106 ddca_sda i/o hdcp slave serial data port a. 1 ddcb_sda i/o hdcp slave serial data port b. 105 ddca_scl i hdcp slave serial clock port a. 144 ddcb_scl i hdcp slave serial clock port b. 2 spdif o spdif digital audio output. 3 i2s0 o i 2 s audio (channel 1 and channel 2). 4 i2s1 o i 2 s audio (channel 3 and channel 4). 5 i2s2 o i 2 s audio (channel 5 and channel 6). 6 i2s3 o i 2 s audio (channel 7 and channel 8). 7 lrclk o data output clock for left and right audio channels. 8 sclk o audio serial clock output. 9 mclkout o audio master clock output. 10 ext_clamp i external clamp signal input for external clock and clamp mode. this is an optional mode of operation for the ADV7441A. 48 ext_clk i clock input for external clock and clamp mode. this is an optional mode of operation for the ADV7441A. 124 rterm i sets internal termination resistance. connect this pin to tgnd using a 500 resistor. 1 g = ground, p = power, i = input, o = output. www..net
ADV7441A rev. b | page 14 of 28 functional overview the following overview provides a brief description of the functionality of the ADV7441A. more details are available in the theory of operation section. analog front end the analog front end of the ADV7441A provides four high quality 10-bit adcs to enable 10-bit video decoding, a multiplexer with 12 analog input channels to enable multisource connection without the requirement of an external multiplexer, and four current and voltage clamp control loops to ensure that dc offsets are removed from the video signal. scart functionality and standard definition rgb overlay with cvbs are controlled by the fb input. hdmi receiver the ADV7441A is compatible with the hdmi 1.3 specification. the ADV7441A supports all hdtv formats up to 1080p and all display resolutions up to uxga (1600 1200 @ 60 hz). the device includes the following features: ? adaptive front-end equalization for hdmi operation with cable lengths up to 30 meters. ? synchronization conditioning for higher performance in strenuous conditions. ? audio mute for removing extraneous noise. ? programmable data island packet interrupt generator. standard definition processor pixel data output modes the ADV7441A features the following sdp output modes: ? 8-/10-bit itu-r bt.656 4:2:2 ycrcb with embedded time codes and/or hs, vs, and field. ? 16-/20-bit ycrcb 4:2:2 with embedded time codes and/or hs, vs, and field. ? 24-/30-bit ycrcb 4:4:4 with embedded time codes and/or hs, vs, and field. component processor pixel data output modes the ADV7441A features single data rate outputs as follows: ? 8-/10-bit 4:2:2 ycrcb for 525i and 625i. ? 16-/20-bit 4:2:2 ycrcb for all standards. ? 24-/30-bit 4:4:4 ycrcb/rgb for all standards. composite and s-vi deo processing the ADV7441A supports ntsc (m/j/4.43), pal (b/d/i/g/h/ m/n/nc/60), and secam (b/d/g/k/l) standards for cvbs and s-video formats. superadaptive 2d, 5-line comb filters for ntsc and pal provide superior chrominance and luminance separation for composite video. the composite and s-video processing functionality also includes fully automatic detection of switching among worldwide standards (pal/ntsc/secam); automatic gain control (agc) with white peak mode to ensure that the video is processed without compromising the video processing range; adaptive digital line length tracking (adllt?); and proprietary architecture for locking to weak, noisy, and unstable sources from vcrs and tuners. the if filter block compensates for high frequency luma attenuation due to the tuner saw filter. other features include chroma transient improvement (cti); luminance digital noise reduction (dnr); color controls for hue, brightness, saturation, contrast; cr and cb offset controls; certified macrovision copy protection detection on composite and s-video for all worldwide formats (pal/ntsc/secam); 4 oversampling (54 mhz) for cvbs, s-video, and yuv modes; line-locked clock output (llc); support for letterbox detection; a free-run output mode for stable timing when no video input is present; a vertical blanking interval data processor; teletext; a video programming system (vps); vertical interval time codes (vitc); closed captioning (cc) and extended data service (eds); wide-screen signaling (wss); a copy generation management system (cgms); clocking from a single 28.63636 mhz crystal; and subcarrier frequency lock (sfl) output for downstream video encoders. the differential gain of the ADV7441A is 0.6% typical, and differential phase is 0.3 typical. www..net
ADV7441A rev. b | page 15 of 28 component video processing the ADV7441A supports 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other hdtv formats; automatic adjustments for gain (contrast) and offset (brightness); manual adjustment controls; analog component yprpb/rgb video formats with embedded synchronization or with separate hs, vs, and cs; and ycrcb-to-rgb and rgb-to-ycrcb conversions by any-to- any, 3 3, color-space conversion matrices. in addition, the ADV7441A features brightness, saturation, and hue controls. standard identification (stdi) enables detection of the component format at the system level, and a synchroniza- tion source polarity detector (sspd) determines the source and polarity of the synchronization signals that accompany the input video. certified macrovision copy protection detection is available on component formats (525i, 625i, 525p, and 625p). when no video input is present, free-run output mode provides stable timing. the ADV7441A supports user-defined pixel sampling for nonstandard video sources and arbitrary pixel sampling for nonstandard video sources. rgb graphics processing the ADV7441A provides 170 msps conversion rate support of rgb input resolutions up to 1600 1200 @ 60 hz (uxga) and automatic or manual clamp and gain controls for graphics models. the rgb graphics processing functionality features contrast and brightness controls, automatic detection of synchronization source and polarity by the sspd block, standard identification enabled by the stdi block, and user-defined pixel sampling support for nonstandard video sources. additional rgb graphics processing features of the ADV7441A include the following: ? sampling pll clock with 500 ps p-p jitter at 170 msps. ? 32-phase dll support of optimum pixel clock sampling. ? color-space conversion of rgb to ycrcb and decimation to a 4:2:2 format for videocentric back-end ic interfacing. ? data enable (de) output signal supplied for direct connection to the hdmi/dvi transmitter ic. general features the ADV7441A features hs, vs, and field output signals with programmable position, polarity, and width; and programmable interrupt request output pins, int1 and int2. the part also offers low power consumption: 1.8 v digital core, 1.8 v analog, and 3.3 v digital input/output and low power power- down mode. the ADV7441A operates over a temperature range of ?40c to +85c and is available in a 144-lead, 20 mm 20 mm, rohs- compliant lqfp. www..net
ADV7441A rev. b | page 16 of 28 theory of operation analog front end the ADV7441A analog front end comprises four 10-bit adcs that digitize the analog video signal before applying it to the sdp or cp. the analog front end uses differential channels connected to each adc to ensure high performance in mixed-signal appli- cations. the analog front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7441A. current and voltage clamps are positioned in front of each adc to ensure that the video signal remains within the range of the converter. fine clamping of the video signals is performed downstream by digital fine clamping in either the cp or sdp. the adcs are configured to run in 4 oversampling mode when decoding composite and s-video inputs. for component 525i, 625i, 525p, and 625p sources, 2 oversampling is performed, but 4 oversampling is available for component 525i and 625i. all other video standards are 1 oversampled. oversampling the video signals reduces the cost and complexity of external antialiasing (aa) filters with the benefit of an increased signal- to-noise ratio (snr). the ADV7441A supports simultaneous processing of cvbs and rgb standard definition signals to enable scart compatibility and overlay functionality. a combination of cvbs and rgb inputs can be mixed and output, as controlled by the i 2 c registers and the fb pin. hdmi receiver the hdmi receiver on the ADV7441A incorporates active equalization of the hdmi data signals. this equalization compen- sates for the high frequency losses inherent in hdmi and dvi cables, especially those with long lengths and high frequencies. it is capable of equalizing for cable lengths up to 30 meters and, therefore, can achieve robust receiver performance at even the highest hdmi data rates. with the inclusion of hdcp, displays can receive encrypted video content. the hdmi interface of the ADV7441A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the hdcp 1.3 protocol. the hdmi receiver also offers advanced audio functionality. the receiver contains an audio mute controller that can detect a variety of selectable conditions that may result in audible extraneous noise in the audio output. upon detection of these conditions, the audio data can be ramped to prevent audio clicks and pops. standard definition processor the sdp section is capable of decoding a large selection of baseband video signals in composite, s-video, and yuv formats. the video standards supported by the sdp include pal (b/d/i/g/h/60/m/n/nc), ntsc (m/j/4.43), and secam (b/d/g/k/l). the ADV7441A automatically detects the video standard and processes it accordingly. the sdp has a 5-line, superadaptive, 2d comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. this highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. the sdp has an if filter block that compensates for attenuation in the high frequency luma spectrum due to a tuner saw filter. the sdp has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue. the ADV7441A implements the patented adllt algorithm to track varying video line lengths from sources such as vcrs. adllt enables the ADV7441A to track and decode poor quality video sources, such as vcrs, and noisy sources, such as tuner outputs, vcd players, and camcorders. the sdp also contains a cti processor. this processor increases the edge rate on chroma transitions, resulting in a sharper video image. the sdp can process a variety of vbi data services, such as teletext, closed captioning (cc), wide-screen signaling (wss), a video programming system (vps), vertical interval time codes (vitc), a copy generation management system (cgms), and an extended data service (xds). the ADV7441A sdp section has a macrovision 7.1 detection circuit that allows it to detect type i, type ii, and type iii protection levels. the decoder is fully robust to all macrovision signal inputs. www..net
ADV7441A rev. b | page 17 of 28 component processor (cp) the component processor section is capable of decoding and digitizing a wide range of component video formats in any color space. component video standards supported by the cp are 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, vga up to uxga at 60 hz, and many other standards. the cp section of the ADV7441A contains an agc block. this block is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct blanking level. automatic adjustments within the cp include gain (contrast) and offset (brightness); however, manual adjustment controls are also supported. if no embedded synchronization is present, the video gain can be set manually. a fully programmable any-to-any 3 3 color-space converter is placed before the cp section. this enables yprpb-to-rgb and rgb-to-ycrcb conversions. many other standards of color space can be implemented using the color-space converter. a second fully programmable any-to-any 3 3 color space converter is placed in the back end of the cp core. this color space converter features advanced color controls such as contrast, saturation, brightness, and hue controls. the output section of the cp is highly flexible. it can be configured in single data rate mode (sdr) with one data packet per clock cycle. in sdr mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. in these modes, hs/cs, vs/field, and de/field (where applicable) timing reference signals are provided. the cp section contains circuitry to enable the detection of macrovision-encoded yprpb signals for 525i, 625i, 525p, and 625p. it is designed to be fully robust when decoding these types of signals. vbi data processor vbi extraction of cgms data is performed by the vbi data processor (vdp) section of the ad7441a for interlaced, progressive, and high definition scanning rates. the data extracted is read back over the i 2 c interface. for more detailed product information about the ADV7441A, send an e-mail to video.products@analog.com or contact a local analog devices sales representative. www..net
ADV7441A rev. b | page 18 of 28 pixel output formatting note that unused pins of the pixel output port are driven with a low voltage. table 8. standard definition pixel port modes (p19 to p0) processor mode/format data port pins p[19:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdp mode 1 video output 8-bit 4:2:2 ycrcb[7:0] C C C C C C C C C C C C sdp mode 2 video output 10-bit 4:2:2 ycrcb[9:0] C C C C C C C C C C sdp mode 3 video output 16-bit 4:2:2 y[7:0] C C crcb[7:0] C C sdp mode 4 video output 20-bit 4:2:2 y[9:0] cb[9:0] sdp mode 5 video output 24-bit 4:4:4 y[7:0] C C cb[7:0] C C sdp mode 6 video output 30-bit 4:4:4 y[9:0] cb[9:0] table 9. standard definition pixel port modes (p29 to p20) processor mode/format data port pins p[29:20] 29 28 27 26 25 24 23 22 21 20 sdp mode 1 video output 8-bit 4:2:2 C C C C C C C C C C sdp mode 2 video output 10-bit 4:2:2 C C C C C C C C C C sdp mode 3 video output 16-bit 4:2:2 C C C C C C C C C C sdp mode 4 video output 20-bit 4:2:2 C C C C C C C C C C sdp mode 5 video output 24-bit 4:4:4 cr[7:0] C C sdp mode 6 video output 30-bit 4:4:4 cr[9:0] www..net
ADV7441A rev. b | page 19 of 28 table 10. component processor pixe l output pin map (p19 to p0) processor 1 mode/format output of data port pins p[19:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cp mode 1 video output 8-bit 4:2:2 2 ycrcb[7:0] C C C C C C C C C C C C cp mode 2 video output 10-bit 4:2:2 2 ycrcb[9:0] C C C C C C C C C C cp mode 3 video output 12-bit 4:2:2 2 ycrcb[11:2] C C C C C C C C C C cp mode 4 video output 12-bit 4:2:2 2 ycrcb[11:4] C C C C C C C C C C C C cp mode 5 video output 12-bit 4:2:2 2 ycrcb[11:4] C C ycrcb[3:0] C C C C C C cp mode 6 video output 16-bit 4:2:2 3 , 4 cha[7:0] (default data is y[7:0]) C C chb/chc[7:0] (default data is cr/cb[7:0]) C C cp mode 7 video output 20-bit 4:2:2 3 , 4 cha[9:0] (default data is y[9:0]) chb/chc[9:0] (default data is cr/cb[9:0]) cp mode 8 video output 20-bit 4:2:22 3 , 4 cha[9:2] (default data is y[9:2]) C C chb/chc[9:2] (default data is cr/cb[9:2]) C C cp mode 9 video output 24-bit 4:2:2 3 , 4 y[11:2] crcb[11:2] cp mode 10 video output 24-bit 4:2:2 3 , 4 y[11:4] C C crcb[11:4] C C cp mode 11 video output 24-bit 4:2:2 3 , 4 y[11:4] C C y[3:0] crcb[3:0] C C cp mode 12 video output 24-bit 4:4:4 3 , 4 cha[7:0] (default data is g[7:0] or y[7:0]) C C chb[7:0] (default data is r[7:0] or cr[7:0]) C C cp mode 13 video output 24-bit 4:4:4 3 , 4 cha[7:0] (default data is g[7:0] or y[7:0]) C C chc[7:0] (default data is b[7:0] or cb[7:0]) C C cp mode 14 video output 24-bit 4:4:4 3 , 4 chc[7:0] (default data is b[7:0] or cb[7:0]) C C cha[7:0] (default data is g[7:0] or y[7:0]) C C cp mode 15 video output 24-bit 4:4:4 3 , 4 chc[7:0] (default data is b[7:0] or cb[7:0]) C C chb[7:0] (default data is r[7:0] or cr[7:0]) C C cp mode 16 video output 30-bit 4:4:4 3 , 4 cha[9:0] (default data is g[9:0] or y[9:0]) chb[9:0] (default data is r[9:0] or cr[9:0]) www..net
ADV7441A rev. b | page 20 of 28 processor 1 mode/format output of data port pins p[19:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cp mode 17 video output 30-bit 4:4:4 3 , 4 cha[9:0] (default data is g[9:0] or y[9:0]) chc[9:0] (default data is b[9:0] or cb[9:0]) cp mode 18 video output 30-bit 4:4:4 3 , 4 chc[9:0] (default data is b[9:0] or cb[9:0]) cha[9:0] (default data is g[9:0] or y[9:0]) cp mode 19 video output 30-bit 4:2:2 3 , 4 chc[9:0] (default data is b[9:0] or cb[9:0]) chb[9:0] (default data is r[9:0] or cr[9:0]) 1 cp processor uses digitizer or hdmi as input. 2 maximum pixel clock rate of 54 mhz. 3 maximum pixel clock rate of 170 mhz (analog digitizer). 4 maximum pixel clock ra te of 165 mhz (hdmi). table 11. component processor pixel output pin map (p29 to p20) processor 1 mode/format output of data port pins p[29:20] 29 28 27 26 25 24 23 22 21 20 cp mode 1 video output 8-bit 4:2:2 2 C C C C C C C C C C cp mode 2 video output 10-bit 4:2:2 2 C C C C C C C C C C cp mode 3 video output 12-bit 4:2:2 2 C C C C C C ycrcb[1:0] C C cp mode 4 video output 12-bit 4:2:2 2 C C C C ycrcb[3:0] C C cp mode 5 video output 12-bit 4:2:2 2 C C C C C C C C C C cp mode 6 video output 16-bit 4:2:2 3 , 4 C C C C C C C C C C cp mode 7 video output 20-bit 4:2:2 3 , 4 C C C C C C C C C C cp mode 8 video output 20-bit 4:2:2 3 , 4 y[1:0] crcb[1:0] C C C C C C cp mode 9 video output 24-bit 4:2:2 3 , 4 C C crcb[1:0] C C y[1:0] C C cp mode 10 video output 24-bit 4:2:2 3 , 4 crcb[3:0] y[3:0] C C cp mode 11 video output 24-bit 4:2:2 3 , 4 crcb[11:4] C C cp mode 12 video output 24-bit 4:4:4 3 , 4 chc[7:0] (for example, b[7:0] or cb[7:0]) C C www..net
ADV7441A rev. b | page 21 of 28 processor 1 mode/format output of data port pins p[29:20] 29 28 27 26 25 24 23 22 21 20 cp mode 13 video output 24-bit 4:4:4 3 , 4 chb[7:0] (for example, r[7:0] or cr[7:0]) C C cp mode 14 video output 24-bit 4:4:4 3 , 4 chb[7:0] (for example, r[7:0] or cr[7:0]) C C cp mode 15 video output 24-bit 4:4:4 3 , 4 cha[7:0] (for example, g[7:0] or y[7:0]) C C cp mode 16 video output 30-bit 4:4:4 3 , 4 chc[9:0] (for example, b[9:0] or cb[9:0]) cp mode 17 video output 30-bit 4:4:4 3 , 4 chb[9:0] (for example, r[9:0] or cr[9:0]) cp mode 18 video output 30-bit 4:4:4 3 , 4 chb[9:0] (for example, r[9:0] or cr[9:0]) cp mode 19 video output 30-bit 4:2:2 3 , 4 cha[9:0] (for example, g[9:0] or y[9:0]) 1 cp processor uses digitizer or hdmi as input. 2 maximum pixel clock rate of 54 mhz. 3 maximum pixel clock rate of 170 mhz (analog digitizer). 4 maximum pixel clock ra te of 165 mhz (hdmi). www..net
ADV7441A rev. b | page 22 of 28 register map architecture the ADV7441A registers are controlled via a 2-wire serial (i 2 c-compatible) interface. the ADV7441A has eight maps, each with a unique i 2 c address. the state of the alsb pin (pin 13) sets bit 2 of each register map address in table 12 . table 12. register map addresses register map default address with alsb = low default address with alsb = high programmable address location where address can be programmed user map 0x40 0x42 not programmable n/a user map 1 0x44 0x46 programmable user map 2, register 0xeb user map 2 0x60 0x62 programmable user map, register 0x0e vdp map 0x48 0x4a programmable user map 2, register 0xec reserved map 0x4c 0x4e programmable user map 2, register 0xea hdmi map 0x68 0x6a programmable user map 2, register 0xef repeater ksv map 0x64 0x66 programmable user map 2, register 0xed edid map 0x6c 0x6e programmable user map 2, register 0xee scl sda sa: programmable sa: programmable sa: programmable sa: programmable sa: programmable sa: programmable sa: programmable reserved map repeater ksv map edid map hdmi map sa: 0x40 vdp map user map 2 user map 1 user map 06914-008 figure 7. register map access through main i 2 c port www..net
ADV7441A rev. b | page 23 of 28 typical connection diagram 06914-009 figure 8. typical connection diagram www..net
ADV7441A rev. b | page 24 of 28 recommended external lo op filter components note that the external loop filter components for the elpf and audio_elpf pins should be placed as close as possible to the res pective pins. the recommended component values are specified in figure 9 and figure 10 . 1.69k ? 82nf 10nf pvdd = 1.8v elpf 70 0 6914-010 figure 9. elpf components 1.5k ? 80nf 8nf pvdd = 1.8v audio_elpf 102 0 6914-011 figure 10. audio_elpf components www..net
ADV7441A rev. b | page 25 of 28 ad9388a ad9388a/ADV7441A evaluation platform analog devices has developed a new evaluation platform for the /ADV7441A decoders. the evaluation platform consists of a motherboard and two daughterboards. the mother- board features a xilinx fpga for digital processing and muxing functions. the motherboard also features three ad9742s (12-bit dacs) from analog devices. this allows the user to drive a vga monitor with just the motherboard and front-end board. the backend of the platform can be connected to a specially developed video output board from analog devices. this modular board features an adv7341 encoder and ad9889b hdmi transmitter. the front end of the platform consists of an eval- ad9388afez_x or eval-ADV7441Afez_x board. this board feeds the digital outputs from the decoder to the fpga on the motherboard. the eval-ad9388afez_x or eval- ADV7441Afez_x board comes with one of the pin-compatible decoders shown in table 13 . table 13. front-end modular board details front-end modular board model on-board decoder hdcp license required eval-ADV7441Afez_1 ADV7441Abstz-170 yes eval-ADV7441Afez_2 ADV7441Abstz-5p no eval-ad9388afez_1 ad9388abstz-170 yes eval-ad9388afez_2 ad9388abstz-5p no eval-ad9388afez_3 ad9388abstz-a5 yes video input board eval-ad9388afez_x or ADV7441Afez_x ad9388a/ADV7441A decoder analog and digital video inputs atv motherboard video output board xilinx fpga vga output avi 168-pin connector avo 168-pin connector hdmi y/c cvbs yprpb ad9889b adv7341 audio 96-pin connector 06914-012 figure 11. functional block diagram of evaluation platform www..net
ADV7441A rev. b | page 26 of 28 outline dimensions compliant to jedec standards ms-026-bfb 051706-a 0.27 0.22 0.17 1 36 37 73 72 108 144 109 top view (pins down) 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 22.20 22.00 sq 21.80 20.20 20.00 sq 19.80 figure 12. 144-lead low profile quad flat package [lqfp] (st-144) dimensions shown in millimeters ordering guide model temperature range packag e description package option ADV7441Abstz-170 1 , 2 ?40c to +85c 144-lead low profile quad flat package [lqfp] st- 144 ADV7441Abstz-110 1 , 2 ?40c to +85c 144-lead low profile quad flat package [lqfp] st- 144 ADV7441Abstz-5p 1 , 3 , 4 ?40c to +85c 144-lead low profile quad flat package [lqfp] st- 144 eval- ADV7441Afez_1 1 , 2 , 5 front end evaluation board eval- ADV7441Afez_2 1 , 4 , 6 front end evaluation board 1 z = rohs compliant part. 2 this part is programmed with internal hdcp keys. customers must have hdcp adopter status (consult digital content protection, llc for licensing requirements) to purchase any components with internal hdcp keys. 3 speed grade: 5 = 170mhz. hdcp functionality: p = no hdcp functionality (pro version). 4 professional version for nonhdcp encrypted applications . purchaser is not required to be a hdcp adopter. 5 front-end board for new evaluation pl atform; fitted with ADV7441Abstz-170 decoder. see the ad9388a/ADV7441A evaluation platfor m section for details on evaluation platform. 6 front-end board for new evaluation platform; fitted with adv 7441abstz-5p decoder. see the ad9388a/ADV7441A evaluation platform section for details on evaluation platform. www..net
ADV7441A rev. b | page 27 of 28 notes www..net
ADV7441A rev. b | page 28 of 28 notes ?2007C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06914-0-7/08(b) www..net

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